To ensure the proper operation of digital circuits, data sent from a transmitting element to a receiving element need to arrive at the receiving element at the proper time. If the data arrives too early, it may erroneously overwrite other data being held in the receiving element. If the data arrives too early, it may prevent the previous data value from being captured by the receiving element. If the data arrives too late, it will not be captured by the receiving circuit element. In effect, for synchronous circuits, data must arrive at a circuit element during a window of time beginning after the receiving element has finished capturing the previous data value and ending at the last point the receiving element can capture the data. The beginning and end of this window are defined, at least in part, by a circuit element's setup time and hold time, respectively.
Associated with setup time and hold time, are setup slack and hold slack. Setup slack is the amount of time data arrives at the receiving element before the receiving element requires the data to arrive (i.e. the end of the window); and hold slack is the amount of time data arrives at a receiving element after the receiving element is required to be ready to receive the data (i.e. the beginning of the window). These concepts are expressed mathematically in the following equations:SlackS=RT−AT; andSlackH=AT−RT;where SlackS is setup slack; SlackH is hold slack; AT is the arrival time of the data at the receiving element; and RT is the required data arrival time, i.e. the end of the window for setup slack, and the beginning of the window for hold slack.
Since both setup and hold slack are so important to circuit functionality, it is common to determine a worst case slack for both the setup and hold circumstances. Worst case setup slack is based on the earliest setup required time, which corresponds to the earliest time the capturing edge may occur. This setup required time answers the question of how much delay a data path can endure at a particular clock frequency. Worst case hold slack is based on the latest hold required time, which corresponds to the latest time the previous capturing edge may occur. This hold required time reveals how much time a receiving element needs to ready itself to receive the data. In either case, if the slack is negative the clock and data arrival events will not occur in the proper order.
Both worst case setup slack and worst case hold slack can be determined based on a static timing analysis of the circuit. Static timing analysis considers only events that occur within a single period of the system clock. For example, if the system clock operates at a frequency of 1 GHz, then static timing analysis considers only events that occur within any 1 nanosecond period. In effect, static timing analysis looks at the end of each data path, to compare the arrival of the data signal to the arrival of the receive clock.
In performing the static timing analysis, two clock edges are used; one simulates the arrival of the data, and the other simulates the triggering edge of the receive clock. To make sure the circuit element being tested will function properly, the two simulated signal edges are adjusted to simulate the most difficult timing requirements the circuit might have to endure. Note that the most difficult timing requirements occur under worst case slack situations. Consequently, the relationship of the triggering edge of the data and the triggering edge of the receiver clock are set to coincide with their relationship during a worst case slack scenario.
In systems using a single master clock to trigger both the data transmitting element and the data receiving element, determining the timing relationship between the data signal (which has the same timing as the data clock) and the receive clock involves comparing two triggering edges of the same clock. Since both triggering edges are part of the same clock signal, determining the relationship between the data signal and the receive clock is relatively straight forward. In multifrequency clock systems, however, determining the relationship between the data signal and the receive clock that corresponds to worst case slack can be more difficult.
Multifrequency clock systems derive their transmit and receive clocks from a single master clock, but for a particular pair of transmit-receive elements, the transmit clock (and hence the data transmitted using the transmit clock) may have a different frequency than the receive clock. This frequency difference can make determining the relationship between the triggering edges of the data signal and the receive clock more difficult, since the timing relationship between the data signal and the receive clock may vary. FIG. 1, which is discussed in greater detail subsequently, illustrates one case in which the timing relationship between a data clock 110 and a receive clock 120 varies.
When performing static timing analysis on multifrequency circuits, designers often employ one of two methods to determine the timing relationship between the data signal and the receive clock. One method is to simply force any receiving elements to be ready to receive data within a single master clock cycle. While this method generally ensures that circuit timing requirements will not be violated, it tends to be overly pessimistic and may require tradeoffs in speed or some other performance factor.
The second method commonly used is illustrated in prior art FIG. 1. The transmit clock 110 and receive clock 120 are unrolled, that is, the edges of each clock are enumerated. The number of clock cycles unrolled corresponds to the number of master clock cycles required to define the least common multiple (LCM) of the two clocks relative to the master clock. For example, consider the case of a master clock 130 having a period m, a transmit clock 110 having a period MX equal to 4m, and a receive clock 120 having a period MR equal to 6m. The LCM of the transmit clock 110 and the receive clock 120 is 12m. Therefore, the clock signals are unrolled to the equivalent of 12 cycles of the master clock 130.
There is, within the unrolled clock cycles, at least one transmit edge 115 that transitions closest in time to the subsequent receive clock edge 125, and one transmit edge 130 that transitions closest in time to the preceding or coincident receive clock edge 135. For the signals shown in FIG. 1, the time t1 (2m) between clock edges 115 and 125 corresponds to the worst case setup slack. The time t2 (0m) between clock edges 130 and 135 corresponds to the worst case hold slack. It is unnecessary to unroll more than the number of clock cycles equal to the LCM (although more are shown), because the relationship between the transmit clock 110 and receive clock 120 starts repeating. For example, the relationship between the clock signals at ½ LCM is the same as the relationship at 1½ LCM, 2½ LCM, and so on.
Once the clocks are unrolled, as illustrated in FIG. 1, the triggering edges of the transmit and receive clocks (assumed for purposes of example to be the rising edges) are compared to determine which rising edge of the receive clock occurs closest to an immediately preceding rising edge of the transmit clock (to determine setup slack). In this example, the second rising edge 125 of the receive clock 120 occurs 2 master clock cycles after the second rising edge 115 of the transmit clock 110. Since no other rising edge of the receive clock 120 occurs closer to any immediately preceding rising edge of the transmit clock 110, it can be safely assumed that under worst case setup slack conditions, the event triggering the receiver (i.e. a rising edge of the receive clock) will occur 2m periods after the transmission triggering event (i.e. a rising edge of the data clock).
A similar procedure can be performed to determine the timing relationship between the data signal and the receive clock under worst case hold slack conditions. Since there is no time difference between rising edge 130 of transmit clock 110 and the closest immediately preceding rising edge of receive clock 120, under worst case hold slack conditions the rising edge of the data signal will occur at the time the receive element is clocked.
Unrolling the clocks to determine the timing relationship between the data signal and the receiver clock signal under worst case slack conditions avoids being overly pessimistic, but unrolling the clocks can be computationally intensive.